// 8-bit Shift-Left Register with Positive-Edge Clock, Asynchronous Parallel Load, Serial In, and Serial Out


module shift (C, ALOAD, enable, SI, D, SO, par_out);
input  C,SI,ALOAD,enable;
input [7:0] D;
output SO;
output [7:0] par_out;
reg [7:0] tmp;

  assign par_out = tmp;

  always @(negedge C or posedge ALOAD)
  begin
    if (ALOAD) begin
    	tmp <= D;
	end else if(enable)
      begin
        tmp <= {tmp[6:0], SI};
      end
  end
  assign SO  = tmp[7];
endmodule