`timescale 1ns / 100ps

///////////////////////////////////////////////////////////////////////////
// Engineer: Alex Freed 
// 
// Create Date:    06/02/2012 
// Module Name:    my6809
// Revision 1 - File Created
// Rev 2 - change the memory remapping
///////////////////////////////////////////////////////////////////////////
module pcpi_intf(
		 output NMI_09,
		 output IRQ_09,
		 output FIRQ_09,
		 output RESET_09,
		 output HALT_09,
		 output U10_1,
		 input BA,
		 input BS,
		 input bus_reset,
		 input bus_rw,

		 inout [7:0]data_09,
		 input [3:0]addr_09, // A12 to A15
		 input VMA,
		 inout BUS_A0,
		 inout BUS_A1,
		 inout BUS_A2,
		 inout BUS_A12,
		 inout BUS_A13,
		 inout BUS_A14,
		 inout BUS_A15,
//		 inout BUS_D7,		 
		 inout BUS_DMA,		 	 
		 inout BUS_IRQ,
		 input DEVSEL,
		 input translate_en
		 );


   reg [7:0] 	       control_reg;
   reg [3:0 ] 	       translated_addr;
   
   wire [2:0] 	       low_addr = {BUS_A2,BUS_A1,BUS_A0};
   wire [7:0] 	       readback = {BA, BS, control_reg[5:0]};
   wire 	       addr15_m = control_reg[7] ? addr_09[3] : ~addr_09[3];
   wire 	       U10_dir = (DEVSEL & bus_rw) | (BUS_DMA & ~bus_rw);

   // (DEVSEL=0 or write) and (DMA or read), i.e. DMA and write
   // or DEVSEL and read

   wire [3:0] high_addr = {addr15_m, addr_09[2:0]};
   wire [3:0] high_addr_out =    translate_en ? translated_addr : high_addr;
   assign BUS_A15 = VMA ? high_addr_out[3] : 1'bz;
   assign BUS_A14 = VMA ? high_addr_out[2] : 1'bz;
   assign BUS_A13 = VMA ? high_addr_out[1] : 1'bz;
   assign BUS_A12 = VMA ? high_addr_out[0] : 1'bz;
   
//   assign BUS_A3 = VMA ? addr_09[3] : 1'bz;   
      
   assign U10_1 = U10_dir;
   assign RESET_09 = control_reg[2];
   assign HALT_09 = control_reg[1] & control_reg[2];
   assign IRQ_09 = control_reg[5];
   assign FIRQ_09 = control_reg[4];
   assign NMI_09 = control_reg[3];
   assign BUS_IRQ = control_reg[0] ? 1'b0 : 1'bz;

   assign BUS_DMA = VMA ? 1'b0 : 1'bz;
   
   assign data_09 = (~DEVSEL & bus_rw) ? readback : 8'hz;
//   assign BUS_D = U10_dir ? 8'hz : data_09;

/*
    
6809	6502
0xxx	1xxx
...	...
7xxx	8xxx
 
8xxx	Dxxx  language card
9xxx	Exxx  language card
Axxx	Fxxx  language card
 
Bxxx	Cxxx	I/O
 
Cxxx	0xxx	zero page, screen, etc.
 
Dxxx	9xxx	OS9 loaded here
Exxx	Axxx	
Fxxx	Bxxx	

*/

   always @(*) 
     case (high_addr)
       4'h0: translated_addr <= 4'h1;
       4'h1: translated_addr <= 4'h2;
       4'h2: translated_addr <= 4'h3;
       4'h3: translated_addr <= 4'h4;
       4'h4: translated_addr <= 4'h5;
       4'h5: translated_addr <= 4'h6;
       4'h6: translated_addr <= 4'h7;
       4'h7: translated_addr <= 4'h8;       
       4'h8: translated_addr <= 4'hd; // memory card space (ROM BASIC)
       4'h9: translated_addr <= 4'he;
       4'ha: translated_addr <= 4'hf;
       4'hb: translated_addr <= 4'hc; // pefipherals at $B000
       4'hc: translated_addr <= 4'h0; // zero page at $C000 in 6809 space
       4'hd: translated_addr <= 4'h9; // OS9 takes these 12K from $9000 in 6502 space
       4'he: translated_addr <= 4'ha;
       4'hf: translated_addr <= 4'hb;
     endcase
            
   
   always @(posedge DEVSEL or negedge bus_reset) begin
     if(bus_reset == 1'b0)
       control_reg <= 8'b0;
     else if(~bus_rw) begin
	    if(data_09[7])
	      control_reg <= control_reg | (1<<low_addr);
	    else
	      control_reg <= control_reg & ~(1<<low_addr);
	 end
   end
      

endmodule