// megafunction wizard: %ALTCLKCTRL%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altclkctrl 

// ============================================================
// File Name: clock_ctrl.v
// Megafunction Name(s):
// 			altclkctrl
//
// Simulation Library Files(s):
// 			cycloneii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.0 Build 33 02/05/2007 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


//altclkctrl clock_type="Global Clock" DEVICE_FAMILY="CYCLONE II" ena_register_mode="falling edge" clkselect ena inclk outclk
//VERSION_BEGIN 7.0 cbx_altclkbuf 2006:05:22:17:40:10:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_stratixiii 2006:10:19:19:28:28:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001


//synthesis_resources = clkctrl 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  clock_ctrl_altclkctrl_cdb
	( 
	clkselect,
	ena,
	inclk,
	outclk) /* synthesis synthesis_clearbox=1 */;
	input   [1:0]  clkselect;
	input   ena;
	input   [3:0]  inclk;
	output   outclk;

	wire  wire_clkctrl1_outclk;

	cycloneii_clkctrl   clkctrl1
	( 
	.clkselect(clkselect),
	.ena(ena),
	.inclk(inclk),
	.outclk(wire_clkctrl1_outclk)
	// synopsys translate_off
	,
	.devclrn(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		clkctrl1.clock_type = "Global Clock",
		clkctrl1.ena_register_mode = "falling edge",
		clkctrl1.lpm_type = "cycloneii_clkctrl";
	assign
		outclk = wire_clkctrl1_outclk;
endmodule //clock_ctrl_altclkctrl_cdb
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clock_ctrl (
	ena,
	inclk,
	outclk)/* synthesis synthesis_clearbox = 1 */;

	input	  ena;
	input	  inclk;
	output	  outclk;

	wire  sub_wire0;
	wire [2:0] sub_wire3 = 3'h0;
	wire [1:0] sub_wire4 = 2'h0;
	wire  outclk = sub_wire0;
	wire  sub_wire1 = inclk;
	wire [3:0] sub_wire2 = {sub_wire3, sub_wire1};

	clock_ctrl_altclkctrl_cdb	clock_ctrl_altclkctrl_cdb_component (
				.ena (ena),
				.inclk (sub_wire2),
				.clkselect (sub_wire4),
				.outclk (sub_wire0));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
// Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "falling edge"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: clock_type STRING "Global Clock"
// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT VCC "ena"
// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
// Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_ctrl.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_ctrl.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_ctrl.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_ctrl.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_ctrl_inst.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_ctrl_bb.v TRUE FALSE
// Retrieval info: LIB_FILE: cycloneii