module spi_mmc(clock,reset,SDO,SDI,SCL,SPI_active,write_data,start,block,read_data,write_strobe, ram_addr);
   input clock;
   input reset,start,block;
   input SDO;
   output SDI;
   output SCL;
   output SPI_active;
   input [7:0] write_data;
   output [7:0] read_data;
   output 	write_strobe;
   output [7:0] ram_addr;



   reg [2:0] 	      bit_cnt;
   reg [9:0] 	      byte_cnt;  // 512 bytes and one extra bit for overflow
   reg [2:0] 	      state;
   reg [2:0] 	      next_state;
   reg [7:0] 	      data;
   reg 		      SCL_high;
   reg 		      write_strobe;

   assign 	      ram_addr = byte_cnt;
   assign 	      read_data = data;
   assign 	      SPI_active = ((state == 1) || (state == 3));


   assign 	      SCL = SCL_high && SPI_active;
  

   always @(posedge clock) begin
      write_strobe <= (bit_cnt == 0) && (state == 3) && ~SCL;
   end

   assign  SDI = (state == 1) ? data[7] : 1'b1;

`ifdef BLOCK_CHANGE
   always @(posedge clock) begin
	case(state)
	0:
		begin
		if(start)
			data <= block ? 8'hff : write_data;
		byte_cnt <= 0;
		bit_cnt <= 0;
		SCL_high <= 1'b0;
		end
	//	SDI <= 1'b1; 
	1:
		begin
		byte_cnt <= 0;
		SCL_high <= ~SCL_high;
		if(SCL_high) begin 
			data <= {data[6:0], SDO};
			if(bit_cnt == 7) begin
				bit_cnt <= 0;
				byte_cnt <= byte_cnt + 1;
			end	else begin
				bit_cnt <= bit_cnt +1;
			end	
		 end
		end
	endcase	
   end
`else

 always @(posedge clock) begin
	if(state == 0)  begin
		if(start)
			data <= block ? 8'hff : write_data;
		byte_cnt <= 0;
		bit_cnt <= 0;
		SCL_high <= 1'b0;
	//	SDI <= 1'b1; 
	end	else begin
		if((state == 1) || (state == 3)) begin
			byte_cnt <= 0;
	//	else 
			SCL_high <= ~SCL_high;
			if(SCL_high) begin 
			   // SDI <= data[7];
				data <= {data[6:0], SDO};
				if(bit_cnt == 7) begin
					bit_cnt <= 0;
					byte_cnt <= byte_cnt + 1;
				end	else begin
					bit_cnt <= bit_cnt +1;
				end	
			 end
		end
	end	
   end


`endif




always @(posedge clock) begin
	state <= next_state;
end

always @(*) begin
	if(reset)
		next_state <= 0;   // start of loading
	else begin
	case (state) 
		0:  if(start) begin
				if(block )
					next_state <= 3;
				else		 
					next_state <= 1;	  // go to 1 after start 
			end else
				next_state <= 0;

		1:  if(byte_cnt == 1) // send bytes, just one for now
			  	next_state <= 2;
			else
				next_state <= 1;

		2:	if(start) 	// wait for start to go inactive
				next_state <= 2;
			else
				next_state <= 0; 
				
				
		3:  if(byte_cnt == 10'h200) 
			  	next_state <= 2;
			else
				next_state <= 3;
				
/*
		3:	if(byte_cnt == 16'h8000) // send command and address
			  	next_state <= 4;
			else 
				next_state <= 3;
	
		4:	next_state <= 4;	
*/
		default :
				next_state <= 0;	
	endcase	
	end	// else reset

end //always		
			
endmodule