module kbd_intf(mclk25, reset_in,PS2_Clk,PS2_Data,scan_addr,scan_res,debug_res0,ASCII_Code,Scan_DAV);

  input mclk25, reset_in;
  input PS2_Clk,PS2_Data;
  input [7:0] scan_addr;
  output [4:0] scan_res;     
  output [6:0] debug_res0;
  output [6:0] ASCII_Code;
  output Scan_DAV;
  
   reg [2:0] kbd_state;	
   reg [2:0] kbd_state_next;
   wire shift,ss;
   reg ctrl;

   
   wire [7:0] Scan_Code;

   wire [2:0] byte;
   wire [2:0] bit;

   reg  [7:0] key_state[0:8];
   wire [4:0] final_code;
   wire bit0, bit1, bit2, bit3, bit4;
   
   reg  [7:0] key_state0;
   reg  [7:0] key_state1;
   reg  [7:0] key_state2;
   reg  [7:0] key_state3;
   reg  [7:0] key_state4;


kbd_transl transl_to_ascii( .shift(shift), .incode(Scan_Code), .outcode(ASCII_Code));

   
   assign scan_res = final_code;

   assign  bit0 =  ~(
	   (~scan_addr[7] & key_state0[7]) | 
	   (~scan_addr[6] & key_state0[6]) | 
	   (~scan_addr[5] & key_state0[5]) |
	   (~scan_addr[4] & key_state0[4]) | 
	   (~scan_addr[3] & key_state0[3]) |
	   (~scan_addr[2] & key_state0[2]) |
	   (~scan_addr[1] & key_state0[1]) | 
	   (~scan_addr[0] & key_state0[0])
   );
   assign  bit1 =  ~(
	   (~scan_addr[7] & key_state1[7]) | 
	   (~scan_addr[6] & key_state1[6]) | 
	   (~scan_addr[5] & key_state1[5]) |
	   (~scan_addr[4] & key_state1[4]) | 
	   (~scan_addr[3] & key_state1[3]) |
	   (~scan_addr[2] & key_state1[2]) |
	   (~scan_addr[1] & key_state1[1]) | 
	   (~scan_addr[0] & key_state1[0])
   );

   assign  bit2 =  ~(
	   (~scan_addr[7] & key_state2[7]) | 
	   (~scan_addr[6] & key_state2[6]) | 
	   (~scan_addr[5] & key_state2[5]) |
	   (~scan_addr[4] & key_state2[4]) | 
	   (~scan_addr[3] & key_state2[3]) |
	   (~scan_addr[2] & key_state2[2]) |
	   (~scan_addr[1] & key_state2[1]) | 
	   (~scan_addr[0] & key_state2[0])
   );
   
   assign  bit3 =  ~(
	   (~scan_addr[7] & key_state3[7]) | 
	   (~scan_addr[6] & key_state3[6]) | 
	   (~scan_addr[5] & key_state3[5]) |
	   (~scan_addr[4] & key_state3[4]) | 
	   (~scan_addr[3] & key_state3[3]) |
	   (~scan_addr[2] & key_state3[2]) |
	   (~scan_addr[1] & key_state3[1]) | 
	   (~scan_addr[0] & key_state3[0])
   );

   assign  bit4 =  ~(
	   (~scan_addr[7] & key_state4[7]) | 
	   (~scan_addr[6] & key_state4[6]) | 
	   (~scan_addr[5] & key_state4[5]) |
	   (~scan_addr[4] & key_state4[4]) | 
	   (~scan_addr[3] & key_state4[3]) |
	   (~scan_addr[2] & key_state4[2]) |
	   (~scan_addr[1] & key_state4[1]) | 
	   (~scan_addr[0] & key_state4[0])
   );



  
   assign final_code = {bit4, bit3, bit2, bit1, bit0};
  
   PS2_Ctrl PS2_Ctrl (
    .Clk(mclk25), 
    .Reset(reset_in), 
    .PS2_Clk(PS2_Clk), 
    .PS2_Data(PS2_Data), 
    .DoRead(DoRead), 
    .Scan_Err(Scan_Err), 
    .Scan_DAV(Scan_DAV), 
    .Scan_Code(Scan_Code)
    );

   spec_trans spec_trans (
    .scan_code(Scan_Code), 
    .byte(byte), 
    .bit(bit),
    .shift(shift),
    .ss(ss)
    );


   assign  DoRead = Scan_DAV;
  // assign debug_res0 = {byte, 1'b0, bit};
   assign debug_res0 = key_state0;

   wire [7:0] shift_bit;
   assign shift_bit = shift ? 1 : 0; // 1 in bit 0 if set
  
  always @(posedge mclk25 ) begin	
     if(reset_in) begin
		ctrl <= 0;
	end
	else begin

    	if( kbd_state == 1) begin

		if(shift)
//	if(scan_code == 8'h66)
			key_state0 <= key_state0 | ( 1 << 0);
			

		case (byte)
		0:  begin 
		    key_state0 <= key_state0 | ( 1 << bit) | shift_bit;
		end
		1:  begin 
		    key_state1 <= key_state1 | ( 1 << bit);
		end
		2:  begin 
		    key_state2 <= key_state2 | ( 1 << bit);
		end
		3:  begin 
		    key_state3 <= key_state3 | ( 1 << bit);
		end
		4:  begin 
		    key_state4 <= key_state4 | ( 1 << bit);
		end
		endcase

	end 
	else if( kbd_state == 6) begin

		if(shift)
	//if(scan_code == 8'h66)
			key_state0 <= key_state0 & ~( 1 << 0);


		case (byte)
		0:  begin 
		    key_state0 <= key_state0 & ~( 1 << bit) & ~shift_bit;
		end
		1:  begin 
		    key_state1 <= key_state1 & ~( 1 << bit);
		end
		2:  begin 
		    key_state2 <= key_state2 & ~( 1 << bit);
		end
		3:  begin 
		    key_state3 <= key_state3 & ~( 1 << bit);
		end
		4:  begin 
		    key_state4 <= key_state4 & ~( 1 << bit);
		end
		endcase

	end
	end
  end //always


 
    always @(posedge mclk25) begin
    	if(reset_in) begin
    		kbd_state <= 0;
		kbd_state <= 0;
	end
    	else begin
		kbd_state <= kbd_state_next;
	end
    end

    always @ (kbd_state or Scan_Code or Scan_DAV) begin
    case (kbd_state)
     0:	if( Scan_DAV)
    		 	kbd_state_next <= 1;
		else
		 	kbd_state_next <= 0;

	1:   // have something, get it
		kbd_state_next <= 2;

	2:   if(Scan_Code == 8'hf0)
			kbd_state_next <= 3;
		else if(Scan_Code == 8'hE0)
			kbd_state_next <= 0;
		else if((Scan_Code == 8'h12) | (Scan_Code == 8'h14) | (Scan_Code == 8'h59)) begin
			 kbd_state_next <= 0;
		end
		else
			kbd_state_next <= 7;

	3:	// was F0	 wait a couple of states for 	Scan_DAV to go down
			kbd_state_next <= 4;

	4:
			kbd_state_next <= 5;

	5:	if( Scan_DAV)	// wait for more
    		 	kbd_state_next <= 6;
		else
		 	kbd_state_next <= 5;

	6:	begin
			kbd_state_next <= 0;
		end
		

	 7:  kbd_state_next <= 0;
	 default: kbd_state_next <= 0;
	endcase
	end




endmodule